Embedded Systems Design, Second Edition

图书介绍

Embedded Systems Design, Second Edition

Publisher:   Newnes
Number Of Pages:   430
Publication Date:   2002-06-15
Sales Rank:   1039438
ISBN / ASIN:   0750655461
EAN:   9780750655460
Binding:   Paperback
Manufacturer:   Newnes
Studio:   Newnes
Average Rating:   3

In this new edition the latest ARM processors and other hardware developments are fully covered along with new sections on Embedded Linux and the new freeware operating system eCOS. The hot topic of embedded systems and the internet is also introduced. In addition a fascinating new case study explores how embedded systems can be developed and experimented with using nothing more than a standard PC.

* A practical introduction to the hottest topic in modern electronics design
* Covers hardware, interfacing and programming in one book
* New material on Embedded Linux for embedded internet systems

Contents:
Preface
Acknowledgements
1 What is an embedded system?
     What is an embedded system?
          Replacement for discrete logic-based circuits
          Provide functional upgrades
          Provide easy maintenance upgrades
          Improves mechanical performance
          Protection of intellectual property
          Replacement for analogue circuits
     Inside the embedded system
          Processor
          Memory
          Peripherals
          Software
          Algorithms
     Examples
          Microcontroller
          Expanded microcontroller
          Microprocessor based
          Board based
2 Embedded processors
     8 bit accumulator processors
          Register models
          8 bit data restrictions
          Addressing memory
          System integrity
     Example 8 bit architectures
          Z80
          Z80 programming model
          MC6800
     Microcontrollers
          MC68HC05
          MC68HC11
          Architecture
     Data processors
          Complex instructions, microcode and nanocode
     INTEL 80286
          Architecture
          Interrupt facilities
          Instruction set
          80287 floating point support
          Feature comparison
     INTEL 80386DX
          Architecture
          Interrupt facilities
          Instruction set
          80387 floating point coprocessor
          Feature comparison
     INTEL 80486
          Instruction set
     Intel 486SX and overdrive processors
     Intel Pentium
     Pentium Pro
          Multiple branch prediction
          Data flow analysis
          Speculative execution
          The MMX instructions
          The Pentium II
     Motorola MC68000
     The MC68000 hardware
          Address bus
          Data bus
          Function codes
          Interrupts
          Error recovery and control signals
     Motorola MC68020
          The programmer’s model
          Bus interfaces
     Motorola MC68030
     The MC68040
          The programming model
     Integrated processors
     RISC processors
          The 80/20 rule
          The initial RISC research
     The Berkeley RISC model
     Sun SPARC RISC processor
          Architecture
          Interrupts
          Instruction set
     The Stanford RISC model
     The MPC603 block diagram
     The ARM RISC architecture
          The ARM register set
          Exceptions
          The Thumb instructions
     Digital signal processors
     DSP basic architecture
     Choosing a processor
          Does it have enough performance?
3 Memory systems
     Memory technologies
          DRAM technology
          Video RAM
     SRAM
          Pseudo-static RAM
          Battery backed-up SRAM
     EPROM and OTP
     Flash
     EEPROM
     Memory organisation
          By 1 organisation
          By 4 organisation
          By 8 and by 9 organisations
          By 16 and greater organisations
     Parity
          Parity initialisation
     Error detecting and correcting memory
     Access times
     Packages
          Dual in line package
          Zig–zag package
          SIMM and DIMM
          SIP
     DRAM interfaces
          The basic DRAM interface
          Page mode operation
          Page interleaving
          Burst mode operation
          EDO memory
     DRAM refresh techniques
          Distributed versus burst refresh
          Software refresh
          RAS only refresh
          CAS before RAS (CBR) refresh
          Hidden refresh
          Memory management
          Disadvantages of memory management
          Segmentation and paging
          Memory protection units
          Cache memory
          Cache size and organization
     Optimizing line length and cache size
     Logical vs physical caches
     Unified versus Harvard caches
     Cache coherency
     Case 1: write-through
     Case 2: write-back
     Case 3: no caching of write cycles
     Case 4: write buffer
     Bus snooping
     The MESI protocol
     The MEI protocol
          Burst interfaces
          Meeting the interface needs
     Big and little endian
     Dual port and shared memory
     Bank switching
     Memory overlays
     Shadowing
     Example interfaces
          MC68000 asynchronous bus
          M6800 synchronous bus
          The MC68040 burst interface
4 Basic peripherals
     Parallel ports
          Multi-function I/O ports
          Pull-up resistors
     Timer/counters
          Types
     8253 timer modes
          Interrupt on terminal count
          Programmable one-shot
          Rate generator
          Square wave rate generator
          Software triggered strobe
          Hardware triggered strobe
          Generating interrupts
     MC68230 modes
     Timer processors
     Real-time clocks
          Simulating a real-time clock in software
     Serial ports
     Serial peripheral interface
     I2C bus
          Read and write access
          Addressing peripherals
          Sending an address index
          Timing
          Multi-master support
     M-Bus (Motorola)
     What is an RS232 serial port?
     Asynchronous flow control
          Modem cables
          Null modem cables
          XON-XOFF flow control
     UART implementations
          8250/16450/16550
          The interface signals
          The Motorola MC68681
     DMA controllers
     A generic DMA controller
          Operation
     DMA controller models
          Single address model
          Dual address model
          1D model
          2D model
          3D model
     Channels and control blocks
     Sharing bus bandwidth
     DMA implementations
          Intel 8237
          Motorola MC68300 series
          Using another CPU with firmware
5 Interfacing to the analogue world
     Analogue to digital conversion techniques
          Quantisation errors
     Sample rates and size
          Irregular sampling errors
          Nyquist’s theorem
     Codecs
          Linear
          A-law and
          -law
          PCM
          DPCM
          ADPCM
     Power control
          Matching the drive
          Using H bridges
          Driving LEDs
          Interfacing to relays
          Interfacing to DC motors
          Software only
          Using a single timer
          Using multiple timers
6 Interrupts and exceptions
     What is an interrupt?
          The spaghetti method
          Using interrupts
     Interrupt sources
          Internal interrupts
          External interrupts
          Exceptions
          Software interrupts
          Non-maskable interrupts
     Recognising an interrupt
          Edge triggered
          Level triggered
          Maintaining the interrupt
          Internal queuing
     The interrupt mechanism
          Stack-based processors
     MC68000 interrupts
     RISC exceptions
          Synchronous precise
          Synchronous imprecise
          Asynchronous precise
          Asynchronous imprecise
          Recognising RISC exceptions
          Enabling RISC exceptions
          Returning from RISC exceptions
          The vector table
          Identifying the cause
     Fast interrupts
     Interrupt controllers
     Instruction restart and continuation
     Interrupt latency
     Do’s and Don’ts
          Always expect the unexpected interrupt
          Don't expect too much from an interrupt
          Use handshaking
          Control resource sharing
          Beware false interrupts
          Controlling interrupt levels
          Controlling stacks
7 Real-time operating systems
     What are operating systems?
     Operating system internals
     Multitasking operating systems
          Context switching, task tables, and kernels
          Time slice
          Pre-emption
          Co-operative multitasking
     Scheduler algorithms
          Rate monotonic
          Deadline monotonic scheduling
          Priority guidelines
     Priority inversion
          Disabling interrupts
          Message queues
          Waiting for a resource
          VMEbus interrupt messages
          Fairness systems
     Tasks, threads and processes
     Exceptions
     Memory model
          Memory allocation
          Memory characteristics
          Example memory maps
     Memory management address translation
          Bank switching
          Segmentation
          Virtual memory
          Choosing an operating system
          Assembler versus high level language
          ROMable code
          Scheduling algorithms
          Pre-emptive scheduling
          Modular approach
          Re-entrant code
          Cross-development platforms
          Integrated networking
          Multiprocessor support
     Commercial operating systems
          pSOS+
          pSOS+ kernel
          pSOS multiprocessor kernel
          pREPC+ runtime support
          pHILE+ file system
          pNA+ network manager
          pROBE+ system level debugger
          XRAY+ source level debugger
          OS-9
          VXWorks
          VRTX-32
          IFX
          TNX
          RTL
          RTscope
          MPV
          LynxOS-POSIX conformance
          Windows NT
          Windows NT characteristics
          Process priorities
          Interrupt priorities
     Resource protection
          Protecting memory
          Protecting hardware
          Coping with crashes
          Multi-threaded software
          Addressing space
          Virtual memory
          The internal architecture
          Virtual memory manager
          User and kernel modes
          Local procedure call (LPC)
          The kernel
          File system
          Network support
          I/O support
          HAL approach
     Linux
          Origins and beginnings
          Inside Linux
          The Linux file system
          The physical file system
          Building the file system
          The file system
     Disk partitioning
          The /proc file system
          Data caching
          Multi-tasking systems
          Multi-user systems
          Linux software structure
          Processes and standard I/O
          Executing commands
          Physical I/O
          Memory management
          Linux limitations
          eLinux
8 Writing software for embedded systems
     The compilation process
          Compiling code
          The pre-processor
          Compilation
          as assembler
          Linking and loading
          Symbols, references and relocation
          Id linker/loader
     Native versus cross-compilers
     Run-time libraries
          Processor dependent
          I/O dependent
          System calls
          Exit routines
     Writing a library
          Creating a library
          Device drivers
          Debugger supplied I/O routines
          Run-time libraries
     Using alternative libraries
          Linking additional libraries
          Linking replacement libraries
     Using a standard library
     Porting kernels
          Board support
          Rebuilding kernels for new configurations
          configA11.h
          config.h
          usrConfig.c
          pSOSystem+
     C extensions for embedded systems
          #pragma interrupt func2
          #pragma pure_function func2
          #pragma no_side_effects func2
          #pragma no_return func2
          #pragma mem_port int2
          asm and _ _asm
     Downloading
          Serial lines
          EPROM and FLASH
          Parallel ports
          From disk
          Ethernet
          Across a common bus
9 Emulation and debugging techniques
     Debugging techniques
          High level language simulation
          Low level simulation
          Onboard debugger
          Task level debugging
          Symbolic debug
          Emulation
          Optimisation problems
          Xray
     The role of the development system
          Floating point and memory management functions
     Emulation techniques
          JTAG
          OnCE
          BDM
10 Buffering and other data structures
     What is a buffer?
          Latency
          Timing tolerance
          Memory size
          Code complexity
     Linear buffers
     Directional buffers
          Single buffer implementation
     Double buffering
     Buffer exchange
     Linked lists
     FIFOs
     Circular buffers
     Buffer underrun and overrun
     Allocating buffer memory
          malloc()
     Memory leakage
          Stack frame errors
          Failure to return memory to the memory pool
          Housekeeping errors
          Wrong memory specification
11 Memory and performance trade-offs
     The effect of memory wait states
     Scenario 1 — Single cycle processor with large external memory
     Scenario 2 — Reducing the cost of memory access
          Using registers
          Using caches
          Preloading caches
          Using on-chip memory
          Using DMA
     Making the right decisions
12 Software examples
     Benchmark example
     Creating software state machines
          Priority levels
          Explicit locks
          Interrupt service routines
          Setting priorities
          Task A highest priority
          Task C highest priority
          Using explicit locks
          Round-robin
          Using an ISR routine
13 Design examples
     Buglar alarm system
          Design goals
          Development strategy
          Software development
          Cross-compilation and code generation
          Porting to the final target system
          Generation of test modules
          Target hardware testing
          Future techniques
          Relevance to more complex designs
          The need for emulation
     Digital echo unit
          Creating echo and reverb
          Design requirements
          Designing the memory structures
          The software design
          Multiple delays
          Digital or analogue adding
          Microprocessor selection
          The overall system design
14 Real- time without a RTOS
     Choosing the software environment
     Deriving real-time performance from a non-real-time system
          Choosing the hardware
     Scheduling the data sampling
     Sampling the data
     Controlling from an external switch
          Driving an external LED display
          Testing
     Problems
          Saving to hard disk
          Data size restrictions and the use of a RAM disk
          Timer calculations and the compiler
          Data corruption and the need for buffer flushing
     Program listing
Index

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